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CY28405-2
Clock Synthesizer with Differential SRC and CPU Outputs
Features
* * * * * * Supports Intel(R) Pentium(R) 4-type CPUs Selectable CPU frequencies 3.3V power supply Nine copies of PCI clocks Four copies of 3V66 with one optional VCH Two copies 48-MHz clock Three differential CPU clock pairs One differential SRC clock Support SMBus/I2 C Byte, Word and Block Read/ Write Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 48-pin SSOP package
CPU x3 SRC x1 3V66 x4 PCI x9 REF x2 48M x2
* * * *
Block Diagram
XIN XOUT
Pin Configuration
VDD_REF REF(0:1)
[1]
XTAL OSC
PLL Ref Freq
Divider Network VDD_CPU CPUT(0:1, ITP), CPUC(0:1, ITP) VDD_SRCT SRCT, SRCC
PLL 1
FS_(A:B) V TP R D T_W G # IREF
VDD_3V66 3V66_(0:2)
PLL2
2
VDD_PCI PCIF(0:2) PCI(0:5)
3V66_3/VCH VDD_48MHz DOT_48 USB_48
P# D
SDATA SCLK
I 2C Logic
*FS_A/REF_0 *FS_B/REF_1 VDD_REF XIN XOUT VSS_REF PCIF0 PCIF1 PCIF2 VDD_PCI VSS_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI VSS_PCI PCI4 PCI5 PD# DOT_48 USB_48 VSS_48 VDD_48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDA VSSA IREF CPUT_ITP CPUC_ITP VSS_CPU CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS_SRC SRCT SRCC VDD_SRC VTT_PWRGD# SDATA* SCLK* 3V66_0 3V66_1 VSS_3V66 VDD_3V66 3V66_2 3V66_3/VCH
~
SSOP-48
* 100k Internal Pull-up Note: 1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
CY28405-2
CypressSemiconductorCorporation Document #: 38-07511 Rev. *C
*
3901NorthFirstStreet
*
SanJose, CA 95134 * 408-943-2600 Revised Spetember 29, 2003
CY28405-2
Pin Description
Pin No. 1 2 4 Name FS_A/REF_0 FS_B/REF_1 XIN Type I/O, SE I/O, SE I Description This pin is the FS_A at power-up and VTT_PWRGD# = 0, then it becomes REF_0 output. (3.3V 14.318-MHz clock output.) This pin is the FS_B at power-up and VTT_PWRGD# = 0, then it becomes REF_1 output. (3.3V 14.318-MHz clock output.) Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection. Connection for an external 14.318-MHz crystal output. CPU Clock Output. Differential CPU clock outputs, see Table1 for frequency configuration.l
5 39, 42, 38, 41, 45, 44 36, 35 26, 29, 30 25 7, 8, 9
XOUT CPUT(0:1), CPUC(0:1), CPUT_ITP, CPUC_ITP SRCT, SRCC 3V66(2:0) 3V66_3/VCH PCI_F(0:2)
O, SE O, DIF
O, DIF O, SE O, SE O, SE O, SE O, SE O, SE I I, PU I I/O, PU I, PU PWR GND PWR GND
Differential Serial Reference Clock. 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. 48- or 66-MHz Clock Output. 3.3V selectable through SMBUS to be 66 MHz or 48 MHz. Default is 66-MHz. Free Running PCI Output. 33-MHz clocks divided down from 3V66. PCI Clock Output. 33MHz clocks divided down from 3V66. Fixed 48-MHz clock output. Fixed 48-MHz clock output. Current Reference. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for PowerDown# active low. 3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E] input (active low). SMBus compatible SDATA. SMBus compatible SCLOCK. 3.3V power supply for PLL. Ground for PLL. 3.3V Power supply for outputs. Ground for outputs.
12, 13, 14, 15, 18, PCI(0:5) 19 22 21 46 20 33 32 31 48 47 3, 10, 16, 24, 27, 34, 40 6, 11, 17, 23, 28, 37, 43 USB_48 DOT_48 IREF PD# VTT_PWRGD# SDATA SCLK VDDA VSSA VDD VSS
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A and FS_B inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A and FS_B input values. For all logic levels of FS_A and FS_B VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled low, all further VTT_PWRGD#, FS_A, and FS_B transitions will be ignored. Once "Test Clock Mode" has been invoked, all further FS_B transitions will be ignored and FS_A will asynchronously select between the Hi-Z and REF/N mode. Exiting test mode is accomplished by cycling power with FS_B in a high or low state.
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Table 1. Frequency Select Table (FS_A FS_B) FS_A 0 0 0 1 1 FS_B 0 B6b7 1 0 B6b7 CPU 100 MHz REF/N 200 MHz 133 MHz Hi-Z SRC 100/200 MHz REF/N 100/200 MHz 100/200 MHz Hi-Z 3V66 66 MHz REF/N 66 MHz 66 MHz Hi-Z PCIF/PCI 33 MHz REF/N 33 MHz 33 MHz Hi-Z REF0 14.3 MHz REF/N 14.3 MHz 14.3 MHz Hi-Z REF1 14.31 MHz REF/N 14.31 MHz 14.31 MHz Hi-Z USB/DOT 48 MHz REF/N 48 MHz 48 MHz Hi-Z
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1 FS_A 0 0 1 FS_B 0 1 0 CPU 200 MHz 400 MHz 266 MHz SRC 100/200 MHz 100/200 MHz 100/200 MHz 3V66 66 MHz 66 MHz 66 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz REF0 14.3 MHz 14.3 MHz 14.3 MHz REF1 14.31 MHz 14.31 MHz 14.31 MHz USB/DOT 48 MHz 48 MHz 48 MHz
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table3. The block write and block read protocol is outlined in Table4 while Table5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from master Data byte from slave - 8 bits Block Read Protocol Description
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Table 4. Block Read and Block Write Protocol (continued) Bit .... .... .... .... .... Block Write Protocol Description Data Byte (N-1) -8 bits Acknowledge from slave Data Byte N -8 bits Acknowledge from slave Stop Bit 47 48:55 56 .... .... .... Block Read Protocol Description Acknowledge from master Data byte from slave - 8 bits Acknowledge from master Data byte N from slave - 8 bits Acknowledge from master Stop
Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 Byte Read Protocol Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Byte Configuration Map
Byte 0: Control Register Bit 7 6 @Pup 0 1 Reserved PCIF PCI Reserved Reserved Reserved Reserved FS_B FS_A Name Reserved, set = 0 PCI Drive Strength Override 0 = Force All PCI and PCIF Outputs to Low Drive Strength 1 = Force All PCI and PCIF Outputs to High Drive Strength Reserved, set = 0 Reserved, set = 0 Reserved, set = 1 Reserved, set = 1 Power-up latched value of FS_B pin Power-up latched value of FS_A pin Description
5 4 3 2 1 0
0 0 1 1 HW HW
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Byte 1: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Name SRCT SRCC SRCT SRCC Reserved Reserved Reserved CPUT_ITP, CPUC_ITP CPUT1, CPUC1 CPUT0, CPUC0 Description Allow control of SRC during SW PCI_STP assertion 0 = Free Running, 1 = Stopped with SW PCI_STP SRC Output Enable 0 = Disabled (three-state), 1 = Enabled Reserved, set = 1 Reserved, set = 1 Reserved, set = 1 CPU_ITP Output Enable 0 = Disabled (three-state), 1 = Enabled CPU(T/C)1 Output Enable, 0 = Disabled (three-state), 1 = Enabled CPUT/C)0 Output Enable 0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRCT, SRCC SRCT, SRCC CPUT_ITP, CPUC_ITP CPUT1, CPUC1 CPUT0, CPUC0 Reserved Reserved Reserved Description SRCT/C Pwrdwn drive mode 0 = Driven in power-down, 1 = three-state in power-down SRC Stop drive mode 0 = Driven in PCI_STP, 1 = three-state in power-down CPU(T/C)_ITP Pwrdwn drive mode 0 = Driven in power-down, 1 = three-state in power-down CPU(T/C)1 Pwrdwn drive mode 0 = Driven in power-down, 1 = three-state in power-down CPU(T/C)0 Pwrdwn drive mode 0 = Driven in power-down, 1 = three-state in power-down Reserved, set = 0 Reserved, set = 0 Reserved, set = 0
Byte 3: Control Register Bit 7 @Pup 1 Name SW PCI STOP Description SW PCI_STP Function 0= PCI_STP assert, 1= PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Reserved PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled
6 5 4 3 2 1 0
1 1 1 1 1 1 1
Reserved PCI5 PCI4 PCI3 PCI2 PCI1 PCI0
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Byte 4: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 1 1 1 Name USB_48 USB_48 PCIF2 PCIF1 PCIF0 PCIF2 PCIF1 PCIF0 Description USB_48MHz Drive Strength Control 0 = Low Drive Strength, 1 = High Drive Strength USB_48MHz Output Enable 0 = Disabled, 1 = Enabled Allow control of PCIF2 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP Allow control of PCIF1 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP Allow control of PCIF0 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled PCIF0 Output Enable 0 = Disabled, 1 = Enabled
Byte 5: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 1 1 1 1 1 DOT_48 Reserved 3V66_3/VCH 3V66_3/VCH Reserved 3V66_2 3V66_1 3V66_0 Name DOT_48MHz Output Enable 0 = Disabled, 1 = Enabled Reserved, set = 1 3V66_3/VCH Frequency Select 0 = 3V66 mode, 1 = VCH (48MHz) mode 3V66_3/VCH Output Enable 0 = Disabled, 1 = Enabled Reserved, set = 1 3V66_2 Output Enable 0 = Disabled, 1 = Enabled 3V66_1 Output Enable 0 = Disabled, 1 = Enabled 3V66_0 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 6: Control Register Bit 7 6 5 @Pup 0 0 0 Reserved Reserved CPUC0, CPUT0 CPUC1, CPUT1 CPUT_ITP,CPUC_ITP SRCT, SRCC PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP Name Reserved, set = 0 Reserved, set = 0 FS_A & FS_B Operation 0 = Normal, 1 = Test mode SRCT/C Frequency Select 0 = 100Mhz, 1 = 200MHz Spread Spectrum Mode 0 = down (default), 1 = center Description
4 3
0 0
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Byte 6: Control Register (continued) Bit 2 @Pup 0 Name PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP REF_1 REF_0 Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On
1 0
1 1
REF_1 Output Enable 0 = Disabled, 1 = Enabled REF_0 Output Enable 0 = Disabled, 1 = Enabled
Byte 7: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 1 0 0 0 Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
Crystal Recommendations
The CY28405-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28405-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Table 6. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Figure 1.Crystal Capacitive Clarification
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Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Clock Chip (CY28405-2) Ci1 Ci2 Pin 3 to 6p
As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors(Ce1,Ce2) should be calculated to provide equal capacitative loading on both sides. Use the following formulas to calculate the trim capacitor values fro Ce1 and Ce2.
Cs1
X1
X2
Cs2 Trace 2.8pF
XTAL Ce1
Ce2
Trim 33pF
Figure 2.Crystal Loading Example
Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) CLe
Total Capacitance (as seen by the crystal)
=
1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2
)
CL ...................................................Crystal load capacitance CLe ........................................ Actual loading seen by crystal ..................................... using standard value trim capacitors Ce .................................................... External trim capacitors Cs............................................. Stray capacitance (trace,etc) Ci ............. Internal capacitance (lead frame, bond wires etc) PD# (Power-down) Clarification The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low `stopped' state. PD# - Assertion When PD# is sampled low by two consecutive rising edges of CPUC clock then all clock outputs (except CPU) clocks must be held low on their next high to low transition. CPU clocks must be hold with CPU clock pin driven high with a value of 2x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
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PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF
Figure 3.Power-down Assertion Timing Waveforms PD# Deassertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 3.0 ms.
Tstable <1.8ms
PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF
Tdrive_PWRDN# <300S, >200mV
Figure 4.Power-down Deassertion Timing Waveforms
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FS_A, FS_B VTT_PWRGD# PWRGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
Wait for VTT_PWRGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PWRGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 5.VTT_PWRGD # Timing Diagram
S1 S2 VTT_PWRGD# = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 6.Clock Generator Power-up/Run State Diagram
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Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 36.9 83.5 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W C/W
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD , VDDA VILI2C VIHI2C VIL VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD IPD Description 3.3 Operating Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current At 200 MHz and all outputs loaded per Table9 and Figure7 PD# asserted, all differential outputs three-stated. except Pull-ups or Pull downs 0 < VIN < V DD IO L = 1 mA IOH = -1 mA 3.3V 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS -0.5 2.0 -5 - 2.4 -10 2 3 - 0.7V DD 0 - - Max. 3.465 1.0 - 0.8 VDD+0. 5 5 0.4 - 10 5 6 7 VDD 0.3V DD 350 1 Unit V V V V V A V V A pF pF nH V V mA mA
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When Xin is driven from an external clock source Min. Max. Unit
47.5
52.5
%
TPERIOD
XIN period
69.841
71.0
ns
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AC Electrical Specifications (continued)
Parameter TR / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIOD TSKEW TCCJ TR / TF TRFM TR TF VHIGH VLOW VO X VOVS VUDS VRB SRC TDC TPERIOD TPERIOD LACC TCCJ TR / TF TRFM TR TF VHIGH VLOW VO X VOVS VUDS VRB Description XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long Term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period Any CPUT/C to CPUT/C Clock Skew CPUT/C Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SRCT and SRCC Duty Cycle 100 MHz SRCT and SRCC Period 200 MHz SRCT and SRCC Period Long Term Accuracy SRCT/C Cycle to Cycle Jitter SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage See Figure 7. Measure SE Math averages Figure 7 Math averages Figure 7 See Figure 7. Measure SE Measured at crossing point VOX Measured at crossing point VO X Measured at crossing point VO X Measured at crossing point VO X Measured at crossing point VO X Measured from Vol= 0.175 to Voh = 0.525V Determined as a fraction of 2*(TR -T F)/(T R +TF ) Math averages Figure 7 Math averages Figure 7 Condition Measured between 0.3V DD and 0.7V DD As an average over 1s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from Vol = 0.175 to Voh = 0.525V Determined as a fraction of 2*(TR -T F)/(T R +TF ) Min. - - - 45 9.9970 7.4978 4.9985 - - 175 - - - 660 -150 250 - -0.3 - 45 9.9970 4.9985 - - 175 - - - 660 -150 250 - -0.3 - Max. 10.0 500 300 55 10.003 7.5023 5.0015 100 125 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 10.003 5.0015 300 125 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 Unit ns ps ppm % ns ns ns ps ps ps % ps ps mV mV mV V V V % ns ns ppm ps ps % ps ps mV mV mV V V V
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AC Electrical Specifications (continued)
Parameter 3V66 TDC TPERIOD TPERIOD THIGH TLOW TR / TF TSKEW TCCJ PCI/PCIF TDC TPERIOD TPERIOD THIGH TLOW TR / TF TSKEW TCCJ DOT TDC TPERIOD THIGH TLOW TR / TF TCCJ TSKEW USB TDC TPERIOD THIGH TLOW TR / TF TCCJ TSKEW REF TDC TPERIOD TR / TF TCCJ TSKEW Description 3V66 Duty Cycle Spread Disabled 3V66 Period Spread Enabled 3V66 Period 3V66 High Time 3V66 Low Time 3V66 Rise and Fall Times Any 3V66 to Any 3V66 Clock Skew 3V66 Cycle to Cycle Jitter PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Enabled PCIF/PCI Period PCIF and PCI High Time PCIF and PCI Low Time PCIF and PCI Rise and Fall Times Any PCI clock to Any PCI Clock Skew PCIF and PCI Cycle to Cycle Jitter Duty Cycle Period USB High Time USB Low Time Rise and Fall Times Cycle to Cycle Jitter Any 48 MHz to 48 MHz clock skew Duty Cycle Period USB High Time USB Low Time Rise and Fall Times Cycle to Cycle Jitter Any 48 MHz to 48 MHz Clock Skew REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Any REF to REF clock skew Condition Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement @1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement @1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement @1.5V Min. 45 14.9955 14.9955 4.9500 4.5500 0.5 - - 45 29.9910 29.9910 12.0 12.0 0.5 - - 45 20.8271 8.094 7.694 1.0 - - 45 20.8271 8.094 7.694 1.0 - - 45 69.827 1.0 - - Max. 55 15.0045 15.0799 - - 2.0 250 250 55 30.0009 30.1598 - - 2.0 500 250 55 20.8396 10.036 9.836 2.0 350 500 55 20.8396 10.036 9.836 2.0 350 500 55 69.855 4.0 1000 500 Unit % ns ns ns ns ns ps ps % ns ns ns ns ns ps ps % ns ns ns ns ps ps % ns ns ns ns ps ps % ns V/ns ps ps
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AC Electrical Specifications (continued)
Parameter Description Condition Min. - 10.0 0 Max. 1.8 - - Unit ms ns ns ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
Table 7. Group Timing Relationship and Tolerances Offset Group 3V66 to PCI Table 8. USB to DOT Phase Offset Parameter DOT Skew USB Skew VCH SKew Typical 0 180 0 Value 0.0ns 0.0ns 0.0ns Tolerance 1000ps 1000ps 1000ps Conditions 3V66 Leads PCI Min. 1.5ns Max. 3.5ns
Test and Measurement Set-up
Table 9. Maximum Lumped Capacitive Output Loads Clock PCI Clocks 3V66 Clocks USB Clock DOT Clock REF Clock Max Load 30 30 20 10 30 Units pF pF pF pF pF
For Differential CPU and SRC Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CPUT
33 49.9 33
TPCB
Measurement Point
2pF
CPUC IREF
475
TPCB
49.9
Measurement Point
2pF
Figure 7.0.7V Load Configuration
Document #: 38-07511 Rev. *C
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CY28405-2
Output under Test Probe
Load Cap
3.3V signals
tDC
-
3.3V
2.0V
1.5V
0.8V 0V
Tr
Tf
Figure 8.Lumped Load For Single-ended Output Signals (for AC Parameters Measurement) Table 10. CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Reference R, I REF - V DD (3*RREF) RREF = 475 1%, IREF = 2.32mA Output Current IOH = 6*IREF VOH @ Z 0.7V @ 50
Ordering Information
Part Number CY28405OC-2 CY28405OC-2T Package Type 48-pin SSOP 48-pin SSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-*C
Purchase of I C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2 C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2 C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07511 Rev. *C Page 15 of 16
2
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semicon ductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi ng so indemnifies Cypress Semiconductor against all charges.
CY28405-2
Document History Page
Document Title: CY28405-2 Clock Synthesizer with Differential SRC and CPU Outputs Document Number: 38-07511 REV. ** *A *B *C ECN NO. 125353 126308 128641 129643 Issue Date 04/15/03 07/16/03 08/27/03 10/01/03 Orig. of Change RGL RGL RGL RGL Description of Change New Data Sheet Fixed typos Specified "Pull-up" function for the SCLK and SDATA in the Pin Description table Changed the voltage threshold on the single-ended output from 2.4V to 2.0 and from 0.4V to 0.8V
Document #: 38-07511 Rev. *C
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